CPU Register - Eflag

> Computer System > Computer - Central processing unit (CPU) > Processor - (Execution) Register

1 - About

The 32-bit EFLAGS register contains:

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3 - Automatic Managment

3.1 - Task

When suspending a task, the processor automatically saves the state of the EFLAGS register in the task state segment (TSS) for the task being suspended.

When binding itself to a new task, the processor loads the EFLAGS register with data from the new task’s TSS.

3.2 - Interrupt or exception handler

When a call is made to an interrupt or exception handler procedure, the processor automatically saves the state of the EFLAGS registers on the procedure stack.

When an interrupt or exception is handled with a task switch, the state of the EFLAGS register is saved in the TSS for the task being suspended.

4 - Management

4.1 - Init

Following initialization of the processor, the state of the EFLAGS register is 00000002H.

4.2 - Reserved

Bits 1, 3, 5, 15, and 22 through 31 of this register are reserved. Software should not use or depend on the states of any of these bits.

4.3 - Move

The following instructions can be used to move groups of flags to and from the procedure stack or the EAX register:

  • LAHF,
  • SAHF,
  • PUSHF,
  • PUSHFD,
  • POPF,
  • and POPFD.
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4.4 - Modification

Some of the flags in the EFLAGS register can be modified directly, using special-purpose instructions. There are no instructions that allow the whole register to be examined or modified directly.

After the contents of the EFLAGS register have been transferred to the procedure stack or EAX register, the flags can be examined and modified using the processor’s bit manipulation instructions (BT, BTS, BTR, and BTC).

4.5 - Show

5 - Documentation / Reference